1. Field of the Invention
Semiconducting conjugated polymer thin-film transistors (TFTs) have recently become of interest for applications in cheap logic circuits integrated on plastic substrates (C. Drury, et al., APL 73, 108 (1998)) and optoelectronic integrated devices and pixel transistor switches in high-resolution active-matrix displays (H. Sirringhaus, et al., Science 280, 1741 (1998), A. Dodabalapur, et al. Appl. Phys. Lett. 73, 142 (1998)). In test device configurations with a polymer semiconductor, inorganic metal electrodes and gate dielectric layers high-performance TFTs have been demonstrated. Charge carrier mobilities up to 0.1 cm2/Vs and ON-OFF current ratios of 106-108 have been reached, which is comparable to the performance of amorphous silicon TFTs (H. Sirringhaus, et al., Advances in Solid State Physics 39, 101 (1999)).
Thin, device-quality films of conjugated polymer semiconductors can be formed by coating a solution of the polymer in an organic solvent onto the substrate. The technology is therefore ideally suited to cheap, large-area solution processing compatible with flexible, plastic substrates. To make full use of the potential cost and ease-of-processing advantages it is desirable that all components of the devices including the semiconducting layers, the dielectric layers as well as the conducting electrodes and the interconnects are deposited from solution.
To fabricate all-polymer TFT devices and circuits the following main problems have to be overcome:                Integrity of multilayer structure: During solution deposition of subsequent semiconducting, insulating and/or conducting layers the underlying layers should not be dissolved, or swelled by the solvent used for the deposition of the subsequent layers. Swelling occurs if solvent is incorporated into the underlying layer which usually results in a degradation of the properties of the layer.        High-resolution patterning of electrodes: The conducting layers need to be patterned to form well-defined interconnects and TFT channels with channel lengths L≦10 μm.        To fabricate TFT circuits vertical interconnect areas (via holes) need to be formed to electrically connect electrodes in different layers of the device.        
2. Description of Related Art
In PCT/GB00/04934 a method is described by which high performance transistors with well-defined and controlled channel lengths of less than 10 μm can be fabricated by solution processing in combination with direct printing. The method (see FIG. 1) is based on patterning the surface energy of the substrate 1 into high surface energy, hydrophilic regions 3 and low surface energy, hydrophobic regions 2. When ink droplets of a conducting ink 4, such as the conducting polymer polyethylenedioxythiophene doped with polystyrene sulfonic acid (PEDOT/PSS), are deposited into the high surface energy regions, the droplets spread inside the hydrophilic region, but their spreading is confined when they hit the hydrophobic barriers (FIG. 1B). Alternatively, the droplets can be deposited directly on top of the hydrophobic barrier region defining the channel length L. If the surface energy of the barrier region is sufficiently low, the ink droplets split in half, and deposit on each side of the barrier. In some situations this process is advantageous compared to the one described in FIG. 1B. For a given droplet volume the minimum width of the source and drain electrodes can be lower by up to a factor of two, because the total ink volume splits in half, and each side of the channel barrier contains only half as much ink as if source and drain areas were filled separately. This process results in the formation of source and drain electrodes 5 with very high resolution. Devices are completed by deposition of a continuous or patterned semiconducting active layer 6, a gate dielectric layer 7, and finally a gate electrode 8.
For many applications the active semiconducting layer needs to be patterned into an active layer island. This is necessary in order to reduce electrical crosstalk and eliminate parasitic leakage currents between neighbouring devices. Even if the semiconducting material is not doped, leakage currents through the semiconducting layer can be significant, in particular for circuits with a high packing density of transistors, such as high resolution active matrix displays. In an active matrix display metallic interconnects for pixel addressing are running across the display. If semiconducting material is present underneath such interconnects lines, parasitic TFT channels can form underneath these interconnect lines, giving rise to non-negligible leakage currents between pixels.
Patterning of a semiconductor active layer island can be achieved by inkjet printing an ink of the semiconducting material on top of the predeposited source-drain array (FIG. 1C). Ideally, in applications where integration density is to be maximised, the active layer island should not be much larger than the source-drain electrode pattern. For many inks this is not easy to achieve. Inks for semiconducting material, such as conjugated polymer semiconductors, are often formulated in highly non-polar solvents, such as xylene or mesitylene. These solvents have low surface energies, hence on wetting substrates droplets of such non-polar ink formulations spread to a large diameter, typically 50-200 μm for inkjet droplet volumes of 10-50 pl. On the other hand, inks of conducting materials, such as PEDOT/PSS in water tend to be formulated in more polar, high surface energy solvents, that spread significantly less. In many situations, the diameter of a dried non-polar semiconducting droplet is significantly larger than the combined width of the source and drain electrodes.
In many applications there is less need for patterning of the gate dielectric layer. A continuous layer of gate dielectric deposited, for example, by processes such as blade, spin, spray or extrusion coating can be useful to allow crossing of interconnects at the source-drain and gate level without the need for deposition of additional insulation layers. However, in the case of unpatterned gate dielectric layers via-hole interconnections are required whenever electrodes/interconnects in a top layer need to be connected electrically to electrodes/interconnects in a bottom layer. If the dielectric layer is patterned, however, such connections can simply be established by printing over the edge of the dielectric pattern (PCT/GB00/04942).